The present invention relates to the field of testing electronic devices. More particularly, the present invention relates to active feedback circuits for minimization of voltage transients during pulsed measurements of semiconductor devices.
Semiconductor devices are used in personal communication devices, satellite communications, and electronic warfare applications. Accurate active-device models are critical for implementing a single-pass circuit design cycle for communications circuits. In order to achieve the highest operational efficiency, power devices are often the last stage of amplification in a transmitting circuit and are often operated in compression. In this mode, higher-order harmonics and intermodulation products that affect signal purity can be generated. The magnitude of the instantaneous voltage and current waveforms at the device nodes, such as forward gate current, can significantly affect device reliability. In order to develop a device model that takes into account the nonlinear behavior of high-power semiconductor devices, both DC I-V and RF S-parameter performance measurements must be obtained. Various test systems have been used to accomplish pulsed I-V testing of high-power semiconductor devices. In order to decrease production costs, more accurate models are needed in order to reduce the design cycle, build, and test. These more accurate models depend on the measurement method. From the measurement results, the parameters of a chosen model can be extracted, and then used in circuit simulators in order to design, analyze, and optimize circuit performance under different operational and environmental conditions. The DC and RF measurements must be made in a pulsed manner in order to avoid destructive thermal stresses. Both the DC and RF measurements must be made in a pulsed manner in order to minimize self-heating and surface-state trap effects. The pulsed measurement, if conducted in less than one microsecond, minimizes channel heating and many surface-state trap effects that will adversely impact the accuracy of the final model. Measurements that occur at less than one microsecond or even faster, are required to extract accurate models. This type of system can cost several hundred thousand dollars.
Referring to FIG. 1, pulsed DC I-V measurements and S parameter measurements have been performed using conventional test configurations, such as the configuration shown. A device under test (DUT) 10, for example, a field-effect transistor (FET) is connected through an input bias tee 12 and an output bias tee 14 to the RF equipment 15. The bias tees 12 and 14 are connected to each of the gate and drain nodes of the DUT 10. The DUT 10 is biased with a DC bias VGS supply 16 connected through an input bias tee sense resistor 17. The input bias tee 18 includes an input bias tee inductor 18 LG that is connected to the gate of the DUT and to coupling capacitor 20, an input bias tee bypass capacitor 22, and the input bias tee sense resistor 17. The output bias tee 14 includes an output bias tee inductor LD 24 that is connected to the drain of the DUT 10 and is also connected to an output bias tee coupling capacitor 26 and an output bias tee bypass capacitor 28, and the output bias tee bias resistor Rb 30. The capacitors 20 and 26 block the dc current and bias voltages from the rf equipment 15, while the inductors 18 and 24 enable a dc bias voltage to be applied to the DUT 10 while presenting a high impedance to the rf signals from the equipment 15. The output bias tee 14 further includes an output bias tee resistor Rb 30 connected to an output sense resistor Rso 32 that is in turn connected to a drain power supply VDD 34. The Rb resistor 30 models parasitic resistance of the output bias tee inductor 24. In most pulsed-IV systems, the drain circuit will require a high-performance and costly pulsed power supply or a well-stabilized constant voltage source that is used to apply the desired drain voltage and simultaneously control transients during a measurement. Conventional test systems apply large voltages to the output bias tee 14 that is connected to the drain of the DUT 10 in order to compensate for the inductive and resistive voltage drops.
A pulsed measurement using the prior art measurement configuration of FIG. 1 initially provides quiescent gate and drain voltages that are applied to the DUT 10. The quiescent gate and drain voltages are applied to the DUT 10, and the DUT is biased beyond cutoff and the drain current is zero. Then, the voltage pulse that is positive relative to the cutoff bias is applied to the gate in order to turn on the DUT 10. A pulse can be applied to the gate or drain or both in order to turn on the DUT 10, while the equipment 15 measures small signal performance for determining the S parameters. In order to control transients at the drain of the DUT 10, the VDD drain power supply 34 may be a pulsed bias supply, such as an HP85120A. The VGS and VDD pulsed power supplies are designed to smoothly ramp the drain current up and then to ramp it down gradually. A VGS pulsed bias supply 16 provides a test pulse the gate of the DUT 10. The VGS pulse causes current to flow in the drain of the DUT 10 during a measurement. When the measurement is conducted in less than one microsecond, self-heating and trap effects are minimized. Throughout the duration of this VGS pulse, a measurement of the DC parameters, including the drain voltage VD, gate voltage VG, gate current IG and drain current ID, as well as the S-parameters can be made. As a consequence of the measurement pulse being applied to the drain and gate of the DUT 10, there is a rapid change in drain current. A change in the current through the LD inductor 24 causes a large negative voltage transient to be produced on the drain of the DUT 10 at the leading edge of the drain-current pulse. Similarly, a large positive voltage transient can be produced at the trailing edge of the drain-current pulse. The value of the voltage transient is LdID/dt where L is the inductance of the bias-tee inductor 24 and dID/dt is slope or rate of change of drain current with respect to time. An I-R voltage drop is produced by the Rb resistance 30 in the output bias tee 14 and any other external resistance that is in series with the drain of the DUT 10. The total drain voltage transient LdID/dt and the DUT voltage and current transients produced can be quite large. Because of the transients produced in the bias tee 14, the drain voltages and currents are not constant within the measurement interval. The I-R voltage drop in the bias tee and any other external resistance leads to inaccurate I-R test results and inaccurate S parameter measurements. Averaging of test results to minimizes measured errors caused by the transients during pulse testing further complicates the testing process. These and other disadvantages are solved or reduced using the invention.
An object of the invention is to provide an active feedback circuit that minimizes damaging voltage transients during pulsed voltage and current (I-V) measurements of high-power semiconductor devices.
Another object of the invention is to reduce drain-voltage transients during pulsed voltage and current measurements of transistors.
Yet another object of the invention is to take measurements just after the rising edge of the gate pulse of a transistor under test to reduce self-heating and trap effects.
The present invention uses three bias tees and places an active feedback circuit around the bias tee providing the drain voltage of a device under test (DUT). A pulsed I-V or pulsed S-parameter measurement can be accomplished within one microsecond of the leading edge of the gate pulse with reduced drain-voltage transients. When the I-V measurements are made quickly after the rising edge of the gate pulse, self-heating and trap effects will be minimized. The gate input pulse can have a small duty cycle to reduce heat in the DUT. A model using parameters extracted from such I-V measurements will then better match the measured performance of the device. The improved model fidelity translates to a more accurate prediction of the circuit performance. The present invention provides an active circuit feedback control of voltage transients with synthesis of low driving point impedance using feedback control that employs parallel combination of amplifiers for wide-bandwidth high-current drive.
The active feedback circuit minimizes voltage transients during pulsed-IV measurements for providing accurate modeling of the DUT. Using the feedback circuit, minimal voltage sag is observed with a reduction in the drain-voltage sag. The effect of the series inductance in the sense bias tee and a series resistor in the drain bias path is effectively removed using active feedback. The significant reduction in the magnitude of the voltage transients keeps the overall system voltages within the safe operating limits of the DUT. The drain current is sensed by measuring the voltage drop across a small sense resistor in the feedback path. Because this small sense resistor is in the feedback path, any voltage drop across this resistance is automatically compensated for by the feedback circuit. A differential amplifier extracts the voltage produced across the small sense resistor for drain-current measurement purposes. The use of the active feedback circuit eliminates the need for a complicated and expensive high-performance, high-current pulsed power supply or well-stabilized voltage sources in the drain circuit. Thus, pulsed-IV measurements can be obtained at significantly lower cost with improved accuracy. These and other advantages will become more apparent in the following detailed description of the preferred embodiment.